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QUAD 2:1 MUX/DEMUX BUS SWITCH
Integrated Device Technology, Inc.
IDT74FST3257 PRELIMINARY
FEATURES:
* Bus switches provide zero delay paths * Extended commercial range of -40C to +85C * Low switch on-resistance: FST3xxx - 5 * TTL-compatible input and output levels * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * Available in QSOP and SOIC
DESCRIPTION:
The FST3257 belongs to IDT's family of Bus switches. Bus switch devices perform the function of connecting or isolating two ports without providing any inherent current sink or source
capability. Thus they generate little or no noise of their own while providing a low resistance path for an external driver. These devices connect input and output ports through an nchannel FET. When the gate-to-source junction of this FET is adequately forward-biased the device conducts or the resistance between input and output ports is small. Without adequate bias on the gate-to-source junction of the FET, the FET is turned off, therefore with no VCC applied, the device has hot insertion capability. The low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero. The FST3257 provides a 4-bit 2:1 multiplexer/demultiplexer. The S pin controls the mux select and the E pin serves as the switch enable.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
I0A ZA I1A I0B-D ZB-D I1B-D 3 Channels S
S I0A I1A ZA I0B I1B ZB GND
1 2 3 4 5 6 7 8
SOIC/QSOP TOP VIEW
16 15 14 SO16-1 SO16-7 13 12 11 10 9
Vcc E I0C I1C ZC 10D I1D ZD
E
3257 drw 01
3257 drw 02
PIN DESCRIPTION
Pin Names I0A-I0D I1A-I1D I/O I/O I/O I I I/O Description Port 0 Port 1 Switch Enable (Active Low) Mux Select Port Z
3257 tbl 01
E
S ZA-ZB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
10.3
DSC-3257/3
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IDT74FST3257 QUAD 2:1 MUX/DEMUX BUS SWITCH
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) Terminal Voltage with Respect to GND TSTG Storage Temperature IOUT Maximum Continuous Channel Current Max. -0.5 to +7.0 -65 to +150 128 Unit V C mA
FUNCTION TABLE(1)
E
H L L L L S X H H L L I0A-D X X X L H I1A-D X L H X X ZA-D Z L H L H
3257 tbl 03
3257 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condiitions for extended periods may affect reliability.
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
2. VCC, Control and Switch terminals.
CAPACITANCE(1)
Symbol CIN CI/O Parameter Control Input Capacitance Switch Input/Output Capacitance Switch Off Conditions(2) Typ. Unit 4
pF pF
3257 tbl 04
NOTES: 1. Capacitance is characterized but not tested 2. TA = 25C, f = 1MHz, VIN = 0V, VOUT = 0V
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol VIH VIL II H II L IOZH IOZL IOS VIK RON Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Voltage High Impedance Output Current (3-State Output pins) Short Circuit Current Clamp Diode Voltage Switch On Resistance(4) VCC = Min., IIN = -18mA VCC = Min., VIN = 0.0V, ION = 30mA VCC = Min., VIN = 2.4V, ION = 15mA VCC = 0V, VIN or VO 4.5V VCC = Max., VI = GND or VCC VCC = Max. Test Conditions(1) Guaranteed Logic HIGH for Control Inputs Guaranteed Logic LOW for Control Inputs VCC = Max. VI = VCC VI = GND VO = VCC VO = GND VCC = Max., VO = GND (3) Min. 2.0 -- -- -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- 300
-0.7
Max. -- 0.8 1 1 1 1 --
-1.2
Unit V V A A mA V A A
3257 tbl 05
5 10 -- 0.1
7 15 1 3
IOFF ICC
Input/Output Power Off Leakage Quiescent Power Supply Current
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Measured by voltage drop between ports at indicated current through the switch.
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IDT54/74FST3257 QUAD 2:1 MUX/DEMUX BUS SWITCH
COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open Enable Pin Toggling 50% Duty Cycle VCC = Max. Outputs Open Enable Pin Toggling (4 Switches Toggling) fi = 10MHz 50% Duty Cycle Min. -- -- Typ.(2) 0.5 30 Max. 1.5 40 Unit mA A/ MHz/ Switch mA
VIN = VCC VIN = GND
IC
Total Power Supply Current (6)
VIN = VCC VIN = GND VIN = 3.4 VIN = GND
--
1.2
1.6
--
1.5
2.4
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fiN) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fi = Input Frequency N = Number of Switches Toggling at fi All currents are in milliamps and all frequencies are in megahertz.
3257 tbl 06
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 5%
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ |QCI| |QCDI| Description Data Propagation Delay I to Z, Z to I(3,4) Switch Multiplex Delay S to I, Z Switch Turn on Delay E to I, Z Switch Turn off Delay E to I, Z(3) Charge Injection, Typical(5,6) Charge Injection, Typical(6,7) Condition(1) CL = 50pF RL = 500 Min.(2) -- 1.5 1.5 1.5 -- -- Typ. -- -- -- -- 1.5 0.5 Max. 0.25 5.2 4.8 5.0 -- -- Unit ns ns ns ns pC pC
3257 tbl 07 NOTES: 1. See test circuit and waveforms. 2. Minimum limits guaranteed but not tested. 3. This parameter is guaranteed by design but not tested. 4. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25 ns for 50 pF load. Since this time is constant and much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5. Measured at switch turn off, load = 50 pF in parallel with 10 m scope probe, VIN = 0.0 volts. 6. Measured at switch turn off through bus multiplexer, (e.g.- I0 to Z = > I1 to Z), load = 50 pF in parallel with 10 M scope probe, VIN at A = 0.0 volts. Charge injection is reduced because the injection from the turn off of the I0 to Z switch is compensated by the turn on of the I1 to Z switch. 7. Characterized parameter. Not 100% tested.
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IDT74FST3257 QUAD 2:1 MUX/DEMUX BUS SWITCH
COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Open
3257 lnk 08 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Switch
Closed
3257 lnk 03
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
3257 lnk 04
PULSE WIDTH
tH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
3257 lnk 03
tSU
tH
PROPAGATION DELAY
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
3257 lnk 06
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 0V
3257 lnk 07
DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V VOH VOL
tPLZ 3.5V 1.5V
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
10.3
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IDT54/74FST3257 QUAD 2:1 MUX/DEMUX BUS SWITCH
COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX FST XX Temp. Range Device Type X Package
SO Q
Small Outline IC (SO16-1) Quarter-size Small Outline Package (SO16-7)
3257
Quad 2:1 Mux/Demux Bus Switch
74
-40C to +85C
3257 drw 08
10.3
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